TSB41LV02

The TSB41LV02 provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV02 is designed to interface with a Link Layer Controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A.

The TSB41LV02 requires only an external 24.576 MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded Strobe and Data information. A 49.152 MHz clocksignal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.

The TSB41LV02 supports an optional isolation barrier between itself and its LLC. When the ISO input terminal is tied high, the LLC interface outputs behave normally. When the ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer
galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in P1394a Supplement (section 5.9.4) (hereafter referred to as Annex J type isolation). To operate with TI Bus Holder isolation, the ISO terminal on the PHY must be high.

Data bits to be transmitted through the cable ports are received from the LLC on two